The present invention relates to CMOS integrated circuits, i.e. to integrated circuits containing both n-channel and p-channel insulated gate field effect devices.
It is widely recognized in the art that it would be highly desirable to achieve practical stacked CMOS integrated circuits, i.e. circuits where a single gate at a single location is capacitatively coupled to control both n-channel and p-channel devices. It is usually assumed that the n-channel devices would be formed in the substrate and the p-channel devices would be formed in polysilicon, although this is not strictly necessary.
Stacked CMOS has the potential to provide extremely dense integrated circuits, and especially to provide extremely dense memory circuits. However, known methods for fabrication of stacked CMOS structures do not permit the overlaid device to be self-aligned. That is, the mask which is used to pattern the channel region of the overlayed polysilicon is applied in a separate masking step from the patterning of the gate which must address this channel. This means that small geometry devices become infeasible, since misalignment between the gate and channel region would introduce a disastrous spread in device characteristics.
Thus it is an object of the present invention to provide a stacked CMOS integrated circuit structure wherein an overlaid polysilicon device has a channel region which is self-aligned to a gate electrode beneath the channel region.
A further difficulty in prior consideration of stacked CMOS devices has been the very low quality of polysilicon-channel devices which have heretofore been attainable. In particular, it is highly desirable to provide a processing technology which provides relatively good device quality in the polysilicon overlaid device.
Thus it is an object of the present invention to provide a stacked CMOS integrated circuit structure which has good device characteristics in the overlaid polysilicon device.
The present invention uses doped oxide sidewall filaments to the first level gate electrode, so that these doped sidewall filaments provide self-aligned doping of the thin second poly level which is used for the overlaid device. Thus, when a separate masking level is used to define the sources and drains of the overlaid device, the masked source/drain regions are connected by source/drain extension regions (doped by diffusion from the doped sidewall oxide) to a lightly doped polysilicon channel region which is self-aligned to the first level gate.
According to the present invention there is provided:
1. A stacked CMOS device comprising:
a substrate; PA1 first and second source/drain regions having a first conductivity type within the surface of said substrate, said source/drain regions defining a channel region therebetween; PA1 an insulated gate level atop said channel region, said insulated gate having approximately vertical sidewalls; PA1 filaments adjacent to said sidewalls of said gate, said filaments of second-dopant; PA1 a second gate insulator atop said gate level; PA1 a thin polysilicon layer atop said second gate insulator and said sidewall filaments, said thin polysilicon layer comprising a second-conductivity type dopant, said thin polysilicon layer being more lightly doped atop said gate level than elsewhere.